1. Field of the Invention
The present invention relates to a semiconductor storage device, such as a static random access memory, and more particularly, to a technique of controlling the voltage of a bit line.
2. Description of the Related Art
In recent years, as miniaturization of semiconductor processes has been advanced, the reliability (resistance to electrical stress, thermal stress or the like) of semiconductor elements has decreased. Also, as the area of a semiconductor storage device has been reduced, it has been increasingly difficult to secure a stable characteristic of, particularly, a memory cell in the semiconductor storage device.
In a typical semiconductor storage device, such as a static random access memory, data is written into a memory cell by causing the potential of either one of a pair of bit lines precharged to the H level to go from the H level to the L level.
In contrast to this, there is a known technique of improving a write characteristic to a memory cell at a low power supply voltage by causing the potential of a bit line during data write to a memory cell to be lower than 0 V (i.e., a negative potential) (see Japanese Unexamined Patent Application Publication No. 2005-071491).